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Hi realthunder, thank you for your answer. I found that for different layout, the amount of decrease to plated hole diameter is different, though the parameter of hole_size_offset is all...

Hi realthunder, you can check with 'blind_buried_vias.kicad_pcb' in your fcad_pcb test folder with the newest kicad.py file. It will generate this error: ``` File "D:/Users/t84201115/AppData/Roaming/FreeCAD/Macro/Read_PCBLayout.FCMacro", line 14, in coppers =...

> Hi realthunder, > > I'm using the latest version of the script with mixed success on the via issues being resolved. > > I am now getting an error...

Hi realthunder, thank you for your contribution on facd_pcb. I think your script to output real 3d layout is till now the only solution. I do not see any intention...