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I am using kicad 6 and 7 (test both), and Freecad 0.19

Another board also has this issue, the only fix is to generate middle layers and top/bot layers separately and then merge. It would be great if we have a new...

Hi realthunder, thank you for checking! Please find one minimum test file here: [test.zip](https://github.com/realthunder/fcad_pcb/files/11899503/test.zip) There are several issues in this practice: 1. I need to at least add one through...

Hi realthunder, thanks for your reponse! From my side, the issue seems to consist:   Thank you for your precious time.

Hi realthunder, Sorry I am not familiar with git, do not know why issue occurs when directly download the complete codes. When I only download kicad.py, it works! Now I...

> Please always provide a sample file showing the problem. In you new added "blind_buried_vias.kicad_pcb" file, if you remove the only though hole via, the fuse will not be made....

Hi realthunder, thnak you! The first two issues are solved. Regarding the last issue, please ref this file: [blind_buried_vias.zip](https://github.com/realthunder/fcad_pcb/files/11931080/blind_buried_vias.zip) In this layout, there are two though vias, one has annular...

Hi realthunder, sorry for the late reply. I have tested your new kicad.py file, this issue is not solved, I think we have different understanding of the concept of "connected...

Hi realthunder, it seems last time I did not update kicad.py successfully. But with the new kicad.py, I still got one bug with the blid_buried_vias.kicad_pcb file. I can successfully generate...

Hi realthunder, I have figured out how to set the thickness of the vias. That is by setting the value of hole_size_offset ``` pcb = kicad.KicadFcad(r'file name',hole_size_offset=0.055) ``` By default,...