Johan Euphrosine

ifp: initialize_floorplan should accept lower bound for relative sizing

2

### Description When using floorplan `relative` floorplan ``` initialize_floorplan -utilization ``` for "very small" design pdngen or placement can fails with the following errors: ``` [ERROR PDN-0185] Insufficient width (16.128...

add support for ESP32

27

using the official esp32 arduino core: https://github.com/espressif/arduino-esp32

- update openlane and open_pdks packages - refactor openlane configs

add chisel notebook

1

It would be nice to have a chisel version of the notebooks that show how to connect chisel verilog codegen to the rest of the open source silicon toolchain. @schoeberl...

first need https://github.com/hdl/conda-eda/pull/327

lvs issue with openlane based notebooks

1

openlane based notebooks like https://github.com/chipsalliance/silicon-notebooks/blob/main/xls-adder-openlane.ipynb seems to be failing LVS with the following error: ``` Cannot find cell __adder__adder in file /content/runs/RUN_2023.04.27_16.16.28/results/signoff/__adder__adder.spice Traceback (most recent call last): File "/content/conda-env/share/openlane/scripts/count_lvs.py", line...

github/workflows: add autotick workflow

2

- fetch latest version from https://anaconda.org/litex-hub/ channel - replace package version in notebooks cells - create PR (that will trigger CI #55) Fixes #60

switch notebook to plain text

2

Using either: https://jupytext.readthedocs.io/ https://nbconvert.readthedocs.io/

add notebooks with gf180mcu SRAM integration

1

#47 is adding a SERV notebook that use an array of registers for the data ram, we should make sure to show integration with GF180MCU sram macros at: https://github.com/google/globalfoundries-pdk-ip-gf180mcu_fd_ip_sram/

add fusesoc variant of the notebooks

2

As discussed in #47, it would be nice to have fusesoc variants of the notebooks that show how to orchestrate openlane along other tasks like simulation and HDL generation.