Johan Euphrosine
Johan Euphrosine
@grotival was mentioning that this would enable the codegen to emit SystemVerilog w/ multiple output ports.
https://internals.rust-lang.org/t/record-types/18258 discuss support for record type in Rust; which could be an inspiration for a future DSLX syntax.
/cc @mikex-oss
related: #843 #906
@dplassgit https://github.com/google/xls/issues/843 only mention inspecting the state while this issue also mention the ability to set it. Maybe I didn't close https://github.com/google/xls/issues/843 at the time as a duplicate because it...
> However, when we're synthesizing hardware, they do not cut out instructions, and instead create (now implicit) muxes between paths that may have very different delays. nit: wouldn't clock (or...
> On the other hand, in the current state without early returns, you may end up doing the assign and mutate pattern as shown in the initial comment above. For...
> Ideally the DSLX magic could also be defined in the main repo per #1451 but that's nice-to-have. +1, I do have it there: https://github.com/google/xls/compare/main...proppy:xls:release but I need to send...
@hzeller do you get the same error when running it on your fork? https://github.com/hzeller/clang-tidy-pr-comments That would help us to rules out project specific configuration issues.
``` The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 06898d0576a1820a131f58b05b6af5f504f080d9, tested: bdc9412b3e468c102d01b7cf6337be06ec6e9c9a) ``` can you share how you installed...