Computer-Organisation

Detailed and step by step implementation of RISC-V CPU from scratch using Verilog. This work is part of my academic course EE2003 (Computer Organisation) during fall semester of 2019.

Contents

• Arithmetic Logic Unit
• Data Memory, Instruction Memory, and Register File
• RISC-V Single-Cycle CPU
• RISC-V 5-stage Pipelined CPU
• Peripheral Memory Association
• RISC-V Pipelined CPU Exception Handling

Final codes for each part is commented denoting the use of particular code block and each part contains a README.md file explaining the problem statement and the approach to solve it.