PothosZynq issues

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Source/Sink for ADC/DAC interface

Hi, We have a small data rate ADC and DACs upto 4MSPS which are interfaced with ZYNQ using LVDS channels. We created the IP which produces ADC Samples over axi-stream...

ujinijoshi

DMA Performance

Hi, I just found your project and was curious if you've done any performance benchmarking of your driver for data transfer rates between CPU/FPGA? I've been working with the zynq-xdma...

austinsteamboat

FPGA logic to create tuser from stat/ctrl user data

We want to create a AXI DMA channel support "lite" that can deal with tuser without requiring the AXI DMA channel mode which requires additional resources and has S2MM limitations...

guruofquality