Yinan Xu

Thanks for the work. This PR looks good. However, I double check the progress of Verilator and find that it would be better to use the predicted stack size provided...

Our patch for Verilator has been accepted. Next release version of Verilator (v5.026) will come with a dynamic stack resizer using `setrlimit`. We've updated difftest to avoid explicit `setrlimit` in...

difftest的README中已经有详细步骤，https://github.com/OpenXiangShan/difftest?tab=readme-ov-file#example-usage 也可以在nutshell/rocket-chip/xiangshan代码中搜索difftest，能展示出所有需要修改的地方，作为案例，https://github.com/search?q=repo%3AOSCPU%2FNutShell%20difftest&type=code

Closed. Please feel free to reopen it if there are future issues

Is it possible to publish Scala packages routinely with necessary dependencies, especially for the reusable parts? That would greatly simplifies other repos dependent on rocket-chip submodules.

> We may also need a config to split XSTop and XSCore to change something outside of XSCore faster. Just leave it as future work. The major issue here is...

> but we need to fix ChiselDB and ConstantIn first. Yes. No matter how we address the multicore issue, we need to ensure they are the same. ChiselDB and ConstantIn...

> I found many things that should be fixed first, especially for ConstantIn and ChiselDB support for hartid from io. FYI, https://github.com/OpenXiangShan/XiangShan/pull/2672

Also, by default, both ChiselDB and constantin are disabled. We can skip them first and fix them in the next step.

https://github.com/OpenXiangShan/XiangShan/pull/1538 introduces this line to mark CSR instructions targeting the mip register as "skip". Here comes why at that time we thought it should be skipped. According to the RISC-V...