Yinan Xu

I'm not sure but it seems from the screenshot it's ok

> Since verilator 5 supports `--timing`, makes rocketchip being able to use pure SystemVerilog+DPI tests to align with commercial tools like VCS. This PR adds a demo DPI test framework...

We are still on the way to upgrading to Chisel 5. Thank you for cc me. We will bump rocket first to the version before new decoder table and then...

For rocket-chip changes, it's recommended to upstream functional changes to chipsalliance.

Chisel just updated the millw script by directly adding it to the git source: https://github.com/chipsalliance/chisel/pull/4119

Recommend using Verilator and running the simulation with `--dump-commit-trace` to see the commit logs.

Your workload is accessing address 0x0 and the CPU keeps raising exceptions on this address. The most likely reason is that, your workload triggers some exception while the exception handler...

Please list or upload full commit logs here for us to verify the reason. However, this issue is mostly unlikely a bug in XiangShan. We request you again to read...

I don't know much about kunminghu. Let current developers have a review

> It can pass a simple zicond test with NEMU difftest I wrote Should we update the default ISA strings in spike and nemu for zicond? We may need to...