Paolo Pisati
Paolo Pisati
While trying to synthesize the cpu16 project, all my toolchains (xilinx ISE and yosys) choke on this: ``` assign IP = cpu.regs[7]; assign zero = cpu.zero; assign carry = cpu.carry;...
Something like: ``` $ cat card-content.txt | trello add-card -b myboard -l mylist "mycard title" ```
Upstream has unexported find_module(): ``` commit 089049f6c9956c5cf1fc89fe10229c76e99f4bef Author: Christoph Hellwig Date: Tue Feb 2 13:13:24 2021 +0100 module: unexport find_module and module_mutex find_module is not used by modular code any...
The [Icesugar](https://github.com/wuxx/icesugar/blob/master/README_en.md) board is a close relative (clone?) of the Icebreaker board: iCE40UP5K, 12Mhz clock, 3 PMODS (well, technically four if you solder one header), 8MB SPI flash, etc and...
learn-fpga/FemtoRV$ make ICESUGAR ... make[2]: Leaving directory '/home/flag/fpga_stuff/learn-fpga/FemtoRV/FIRMWARE/CRT' ==== Generated femtorv32 libs. make[1]: Leaving directory '/home/flag/fpga_stuff/learn-fpga/FemtoRV/FIRMWARE' make: *** No rule to make target 'FIRMWARE/firmware.hex', needed by 'ICESUGAR.synth'. Stop.
I tried both the prebuilt binary and to rebuild it myself - no output on the usb-c serial: @cdone:1 @reset @cdone:0 @prog [0x00000000] @prog [0x00010000] @start @cdone:1 and if i...
### What reproduces the bug? Provide code if possible. Issue: variable.tracepoint test behaves randomly, sometimes if fails, sometimes it passes - just runtime manually a 2/3 times to see all...