piegames
piegames
It is not the first time it happens to me, but last time I was unsure about my sanity. Basically, when I have a debugging issue and set `withWave` or...
While playing around with `Mem`, I came across some questionable behavior that I'd like to discuss: 1. A synthesized `write` port with `enable` signal will continue to write during resets....
May I present you a foot gun: ``` val tuple = TupleBundle2(U(4, 32 bits), True) ``` Contrary to what one would expect, this code does **not** initialize `tuple` with `4`...
I don't know how, but I happened to produce a `switch` statement with the following syntax: ```scala switch(number) { 0 -> {}, 1 -> {}, 2 -> {}, } ```...
I can create a component with the name `Accumulator (128 bits)`. However, this will be used directly in Verilog without escaping, and thus produce syntax errors. Either restrict `setDefinitionName` to...
Kind of a sub-thread of #137 specific to resets. At the moment, all statements are generated implicitly inside a block that only runs when the system is running. This kind...
The generated Verilog code contains a header like this: ```Verilog // Generator : SpinalHDL v1.3.9 git head : 0f14fcc31e1099ab7fb106009a605d0d6e7be21a // Date : 12/03/2020, 23:01:57 // Component : SlowdownTest ``` Including...
I'my currently trying out fix point operations and I'm missing a few features: - Widen a fix point number (both the exponent and the resolution, separately) - Cast between signed...
I have the simple problem, that I want to connect my 12 bit address space AXI slave to a 32bit AXI master. The wires can simply be `resized` without any...
AXI4 and it's lite variants are not two distinct specifications. In reality, it is more like AXI is a set of features, where AXI lite uses less of them. Therefore,...