Peter Hizalev
Peter Hizalev
Can you share the model?
Please try running: ``` tensil compile -m resnet50_model.pb -a ./arch/ultra96v2.tarch -o "Identity" -v true -s true ``` You can also replace `ultra96v2` with desired architecture definition.
This comment is for us to plan compiler fixes to accommodate this model. There are several issues I am seeing right away: - [x] Frontend node traversal gets into seemingly...
This can happen if Tensil Compute Unit (TCU) is not functioning correctly. Did you follow the steps to create block design and the bitstream in Vivado?
Can you also share exported block design? (click _Export -> Export Block Design_ while having block design open)
I successfully implemented the bitstream in Vivado based on your design script, I see no errors in design and timing is met. I will test on Ultra96 board next.
I am attaching the bitstream and hwh files made by implementing your block design in Vivado. [tensil_ultra96v2_test.zip](https://github.com/tensil-ai/tensil/files/9396206/tensil_ultra96v2_test.zip) To load it in the PYNQ code: ```python overlay = Overlay('/home/xilinx/tensil_ultra96v2_test.bit') tcu =...
Can you give an example of request that is timing out?
Issue #1 is about _requests_ with empty body, not responses. So not an issue in your case. I do see message queue for `gun_sup` at 152. Can you correlate size...
Can you try one thing: define identical configuration for 4 pools (e.g. app0, app1 etc). Then use random pool when requesting. Do your numbers change?