Paul Scheffler

Which version are you using exactly? Our doc specifies `>= 11.2.0`. Sadly, the ISA strings accepted by RISC-V GCC are not stable across versions; there's nothing we can do about...

Hi, sorry for the late reply. We are currently working on this together with a descriptor-based frontend; you may want to follow #183 .

Hi, Thanks for reporting this issue. In principle, AXI data widths of more than 64 bits should be supported, but we indeed did not test this extensively. I assume the...

Hi, Apologies for the delay. If I understand correctly, the write-back (WB) data cache of CVA6 indeed does not support different datawidths, only the write-through (WT) cache. You should be...

Would you be interested in retargeting this to `main`? I cannot adopt the LLC partitioning change as is (#74 seems to be stuck in serious limbo) but I am generally...

Then that sounds like a path forward. Kinda. Updated the PR message. There is an LLC PR for partitioning (https://github.com/pulp-platform/axi_llc/pull/10), but either something is *bizarrely* wrong with it (5k+ changes)...

Currently, you can instantiate multiple cores in Cheshire *without* hardware coherency, but the baremetal software setup for this is still in the works (#169). That said, you can just roll...

I have a question regarding your application here: can you use `slink_elf_preload` instead? That task already has a parametric maximum burst size (defaults on legal 1 KiB) and splits long...

Reviving this PR as it may be best to add Litmus tests separately after all. Still a draft.

Closes #212.