Paolo Mantovani
Paolo Mantovani
Hello, thank you for reaching out. I have not run into this issue yet and I have only scratched the surface of this driver in order to port it to...
Right now I have a script for SystemC and C based accelerators and this should be able to generate Chisel code as well in the future. Were you suggesting to...
I see. We should spec this out starting from the full example. I will push the script soon. With respect to application and device driver there is very little to...
First draft of the script is available on the branch 'devel'
SystemC flow and Vivado HLS flows are merged. The Vivado HLS flow still requires fixes for some corner case at the interface.
Just a little extra info on the topic: I tried using xsim in the past, but I faced a lot of issues. In the end, once I managed to get...
@Kendidi we should try to keep issues separate by topic. I am replying to you on #66 but I can't mention you there, because you haven't posted on that issue...
Hello and thank you for writing! In general, supporting a different development board is not too complex, but there are three requirements: 1. The FPGA (programming logic) must have direct...
Hi @simplelins. Thank you for writing. Bumping the IP definitions and the scripts for Vitis 2020 is not difficult. For the most part it just requires to change IP revision...
Hi @simplelins: are you still attempting to create a template design for the Alveo board? Please let us know if you need additional information or help.