Bassant Hassan

@maliberty The power supply pins; `VDD VSS DVDD DVSS`

The source layout has the pins at the boundary, but I extended them a bit outside the boundary when the pdn connections didn't work. I thought avoiding having the stripes...

@arlpetergadfort Hii, I wanted to ask, did you get a chance to take a second look at this? thanks

@RTimothyEdwards PR #209 is related to PrimeTime signoff of the re-implemented blocks. PT doesn't generate `spef`, only `lib` and `sdf`

issue #199 PR includes only the re-implemented blocks. Other blocks are still wip

- LVS, DRC, and STA of all re-implemented blocks and top-level caravel are added to `./signoff//signoff.rpt` using Caravel [signoff automation script](https://github.com/efabless/caravel/blob/caravel_redesign/scripts/signoff_automation.py) - CVC is performed using Mitch's custom script and...

Google issue tracker: [#7](https://github.com/google/globalfoundries-pdk-libs-gf180mcu_fd_io/issues/7)

The updated hierarchy used macros libs could be found [here](https://github.com/efabless/caravel/tree/main/lib)

[efabless/timing-scripts](https://github.com/efabless/timing-scripts)

Volare issue tracker: [#31](https://github.com/efabless/volare/issues/31)