p0nce
p0nce
intel-intrinsics allows some instruction to shift by more than size in bits, because it has actually no runtime cost in inline optimized code. Not sure how evil that is.
The question (with regards to shifting) is that D says it's UB, but the x86 instruction is well defined. And I've said at Dconf that "intel-intrinsics semantics is always modelled...
Also same question with _mm_alignr_pi8 / _mm_alignr_epi8 with larger counts. If we make this UB, might be better for arm vs x86.
It can build if you do that: ``` "derelict-sdl2":"==2.1.2", "derelict-gl3":"==1.0.21", "derelict-util":"==2.0.4" ``` proper fix would be to move to bindbc I guess
Also DMD: use core.simd instead of emulation when available.
Blocked by #59
Each version of DMD bring regressions when SIMD vectors are actually used. It's a maintenance burden.
D_SIMD finally enabled in intel-intrinsics v1.9, when DMD 2.099+ is used. Let's see what happens next.
8 hours later I was asked to remove it. 4 bugs are kinda blockers for D_SIMD to happen (well, more will be found as translation progress, but also perf will...
4 more issues fixed by core. https://forum.dlang.org/post/[email protected]