Oliver Keller

a 3D assembly view would be so nice and especially useful for electronic beginners! For this beginner-friendly project I've used scripts to generate resistor models with colour bands:  In...

python3 (with functional pip) and/or CLI tools that allow folder syncing via webdav/dropbox etc. on the tablet

ups, how embarrassing! thanks for pointing it out. This invalidates my entire request of course. Somehow I had assumed only the packages listed on the toltec page would be part...

+1 for Global access control as it is done in openHAB. we want to use openhab2 in an organization-wide newtork do to show control for visit points and exhibitions.

@kaikreuzer sorry, that's way out of my skills. I come from an embedded C world with precicely defined typing etc. and struggle a lot these days in just getting my...

I still saw this issue with $glbnet$eth_clocks_rx$TRELLIS_IO_IN failing well below 100 MHz after all those improvements and even on a Butterstick board using ECP5 with speed grade 8. It took...

@rowanG077 I meant the test bench folder projects, for example https://github.com/enjoy-digital/liteeth/blob/master/bench/butterstick.py

32-bit data width can be changed from the 8-bit default, this works: ``` self.add_etherbone(phy=self.ethphy, buffer_depth=255, data_width=32) ``` I just wanted to highlight that current ECP5 test bench examples still report...

the phy's configuration straps could be of concern, depending on the board/pmod wiring. see for example the notes for ulx3s https://github.com/emard/ulx3s-misc/tree/master/examples/eth/rmii/proj and related discussion: https://github.com/emard/ulx3s/issues/14#issuecomment-856644033 since you connected RST, you...

In the Makefile, [where write_cxxrtl is called](https://github.com/tomverbeure/cxxrtl_eval/blob/a406543aa337c41f73ebfb2254e796f89ede652a/blink_basic_vhdl/Makefile#L14), you have to add `-O4` or a lower number as a parameter just before the final `$@`. The default optimization level `-O6` seems...