Benjamin Herrenschmidt

Not terribly hard. I assume the UART has the same interface as the LiteX UART ? So we'd need to instanciate the same driver more/less. The main issue is going...

@enjoy-digital This is suitable for tightly coupled embedded devices, but will not scale. Since it's unrealistic to have new PCI IDs for every possible FPGA device configuration, I think there's...

I don't have a strong opinion... either of the above works, whatever is the most realistic to implement :-) As for LiteX generating GHDL, that's a migen issue, I don't...

Same here :-) Things like pesign (and associated RPM macros) more/less hard wire that the socket is in /var/run and I wouldn't be surprised if that is the only case....

I could try to submit patches to pesign to make the socket path an optional argument, but one would have to also change all the related RPM macros from hell,...

This looks stale, should we file an issue with LiteX ?

This isn't how you build it :-) It's built by litedram/gen-src/generate.py The build process uses a combination of sources in LiteX itself and the stuff in litedram/gen-src/sdram_init. Since LiteX tends...

(Mikey, you can probably close this)

Why remove it ? it would make things more messy ... it contains the bits that generate.py uses (along with LiteX) to generate the inits ... But yes, adding a...

we should also remove the copy of bin2hex in there :)