cvfpu
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Bug report: Floating conversion from double to simple infinity sets a lot of ones in the mantissa
Hi there!
I've detected a bug in CVFPU.
Brief bug description
A conversion of +inf from double to simple sets a lot of bits in the mantissa, unexpectedly. I have found it through cva6.
Example instance
Here is an example RISC-V (rv64imfd) snippet:
.section ".text.init","ax",@progbits
.globl _start
.align 2
_start:
# Enable the FPU
li t0, 0x2000
csrs mstatus, t0
csrw fcsr,x0
la t0, .fdata0
fld ft0, (t0)
fcvt.s.d ft1, ft0, rdn
li t0, 0x18
fsd ft1, (t0)
sw x0, 0(x0)
infinite_loop:
j infinite_loop
.section ".fdata0","ax",@progbits
.8byte 0x7ff0000000000000
Expected and actual results
We expect ft1= 0xffffffff7f800000.
. I verified this with Spike.
However, CVA6 gives ft1= 0xffffffff7f7fffff.
.
Thanks! Flavien