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Published 20 hours ago • verified publisher icon openhwgroup
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Metadata

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

Results 105 cve2 issues
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Project Freeze

LeeHoff avatar LeeHoff

task

Coverage signoff

Review coverage holes from “sign-off” regression Review any open issues

LeeHoff avatar LeeHoff

task

Execute and debug ISA tests to get 100% pass rate for all

LeeHoff avatar LeeHoff

task

Port existing RISC-V ISA environment from E40*

LeeHoff avatar LeeHoff

task

Measure E20 performance metrics on select benchmarks, e.g., CoreMark, ULPBench, Dhrystone

joecircello avatar joecircello

task

Core Complex Design Completion

LeeHoff avatar LeeHoff

task

Core complex verification

TB creation, Test creation, Coverage creation

LeeHoff avatar LeeHoff

task

Integration of components (CLIC, Debug)

1 comment

LeeHoff avatar LeeHoff

task

RTL design of OBI2AHB

Complete

LeeHoff avatar LeeHoff

task

RISC-V ISA Compliance

LeeHoff avatar LeeHoff

task

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verified publisher icon openhwgroup

Metadata

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

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