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Published 20 hours ago • verified publisher icon openhwgroup
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Metadata

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

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JEDEC manufacturer ID for CV32E20

1 comment

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Values for MVENDORID, MARCHID and MIMPID

1 comment

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Ensure CORE-V-VERIF Makefiles support both SNPS VCS and Siemens Questa

1 comment

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Spike UVM Sequence item for RISC-V instructions

1 comment

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UVM Sequence item for RISC-V instructions

2 comment

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Port to CORE-V-VERIF

1 comment

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Clean up and Complete Input/Output ports of CVE2

1 comment

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Expose core state (user or machine mode) to top-level output ports

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Adopt Smrnmi

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Implement the still to be ratified "Standard Extension for Resumable Non-Maskable Interrupts". See the RISC-V Privileged Specification (Document version 20211203), Chapter 4.

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task

Remove mcontext and scontext registers

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verified publisher icon openhwgroup

Metadata

The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.

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