cve2
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The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.
### Bug Description This issue is motivated by a discussion on pull-request #273. As of this writing the latest [ratified specifications](https://riscv.org/technical/specifications/) are `20240411`. Given that this core is multiple months...
### Bug Description Hi @mario. In #184 you indicated that compiling RVFI requires inclusion of the cv32e20-dv environment. This sounds odd. Looking at [cve2_cs_registers.sv](https://github.com/openhwgroup/cve2/blob/7f3bb9fcb28e55b227c966734d8e81ddef58b7e3/rtl/cve2_cs_registers.sv#L1482) we see: ``` `ifdef RVFI logic...
### Task Description Current implementation of RNMIs is based on a custom Ibex implementation. When Smrnmi is ratified, move to the standard version. ### Description of Done Compliance to Smrnmi,...