Segmentation fault using QuestaSim

[davidmallasen]

Hello,

The latest version of the repo (8d893fb647d758bed5876307c64caa6adbc89f97) triggers a segmentation fault when trying to simulate using QuestaSim. This does not happen with commit 00236be3d8552f93a0bebda8f9820ec54b64a000 . The steps I have followed are:

git clone https://github.com/openhwgroup/cva6.git
cd cva6
git submodule update --init --recursive

mkdir tmp

echo '
#include <stdio.h>

int main(int argc, char const *argv[]) {
    printf("Hello CVA6!\\n");
    return 0;
}' > hello.c

riscv64-unknown-elf-gcc hello.c -o hello.elf

make sim elf-bin=$RISCV/riscv64-unknown-elf/bin/pk target-options=hello.elf batch-mode=1

This outputs the following:

Makefile:151: XCELIUM_HOME not set which is necessary for compiling DPIs when using XCELIUM
vlib work
vlog +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+WT_DCACHE+RVFI_TRACE -work work /home/david/cva6/core/include/cv64a6_imafdc_sv39_config_pkg.sv /home/david/cva6/core/include/riscv_pkg.sv /home/david/cva6/corev_apu/riscv-dbg/src/dm_pkg.sv /home/david/cva6/core/include/ariane_pkg.sv /home/david/cva6/core/include/ariane_rvfi_pkg.sv /home/david/cva6/core/include/wt_cache_pkg.sv /home/david/cva6/core/include/cvxif_pkg.sv /home/david/cva6/corev_apu/axi/src/axi_pkg.sv /home/david/cva6/corev_apu/register_interface/src/reg_intf.sv /home/david/cva6/core/include/axi_intf.sv /home/david/cva6/corev_apu/tb/rvfi_pkg.sv /home/david/cva6/corev_apu/tb/ariane_soc_pkg.sv /home/david/cva6/corev_apu/tb/ariane_axi_soc_pkg.sv /home/david/cva6/core/include/ariane_axi_pkg.sv /home/david/cva6/core/include/std_cache_pkg.sv /home/david/cva6/core/fpu/src/fpnew_pkg.sv /home/david/cva6/common/submodules/common_cells/src/cf_math_pkg.sv /home/david/cva6/core/cvxif_example/include/cvxif_instr_pkg.sv /home/david/cva6/core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv  +incdir+common/submodules/common_cells/include/  +incdir+corev_apu/axi/include/  +incdir+corev_apu/register_interface/include/ -suppress 2583
** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
# vcom -64 -nologo -quiet -2008 -work work -pedanticerrors 
vlog +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+WT_DCACHE+RVFI_TRACE -timescale "1ns / 1ns" -work work /home/david/cva6/core/include/instr_tracer_pkg.sv /home/david/cva6/common/local/util/instr_tracer_if.sv /home/david/cva6/common/local/util/instr_tracer.sv /home/david/cva6/corev_apu/src/tech_cells_generic/src/cluster_clock_gating.sv /home/david/cva6/corev_apu/tb/common/mock_uart.sv /home/david/cva6/common/local/util/sram.sv  +incdir+common/submodules/common_cells/include/  +incdir+corev_apu/axi/include/  +incdir+corev_apu/register_interface/include/ -suppress 2583
** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
# Suppress message that always_latch may not be checked thoroughly by QuestaSim.
vcom -64 -nologo -quiet -2008 -work work -pedanticerrors /home/david/cva6/corev_apu/fpga/src/apb_uart/src/apb_uart.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/uart_transmitter.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/uart_interrupt.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/slib_mv_filter.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/slib_counter.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/slib_clock_div.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd /home/david/cva6/corev_apu/fpga/src/apb_uart/src/uart_baudgen.vhd
# vcom -64 -nologo -quiet -2008 -work work -pedanticerrors 
vlog +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+WT_DCACHE+RVFI_TRACE -timescale "1ns / 1ns" -work work -pedanticerrors /home/david/cva6/core/serdiv.sv /home/david/cva6/core/ariane_regfile_ff.sv /home/david/cva6/core/issue_stage.sv /home/david/cva6/core/cvxif_fu.sv /home/david/cva6/core/branch_unit.sv /home/david/cva6/core/dromajo_ram.sv /home/david/cva6/core/controller.sv /home/david/cva6/core/commit_stage.sv /home/david/cva6/core/re_name.sv /home/david/cva6/core/mult.sv /home/david/cva6/core/csr_buffer.sv /home/david/cva6/core/decoder.sv /home/david/cva6/core/ex_stage.sv /home/david/cva6/core/scoreboard.sv /home/david/cva6/core/store_unit.sv /home/david/cva6/core/ariane.sv /home/david/cva6/core/axi_adapter.sv /home/david/cva6/core/fpu_wrap.sv /home/david/cva6/core/csr_regfile.sv /home/david/cva6/core/load_store_unit.sv /home/david/cva6/core/id_stage.sv /home/david/cva6/core/multiplier.sv /home/david/cva6/core/store_buffer.sv /home/david/cva6/core/compressed_decoder.sv /home/david/cva6/core/axi_shim.sv /home/david/cva6/core/alu.sv /home/david/cva6/core/instr_realign.sv /home/david/cva6/core/perf_counters.sv /home/david/cva6/core/cva6.sv /home/david/cva6/core/amo_buffer.sv /home/david/cva6/core/load_unit.sv /home/david/cva6/core/issue_read_operands.sv /home/david/cva6/core/fpu/src/fpnew_fma.sv /home/david/cva6/core/fpu/src/fpnew_opgroup_fmt_slice.sv /home/david/cva6/core/fpu/src/fpnew_divsqrt_multi.sv /home/david/cva6/core/fpu/src/fpnew_fma_multi.sv /home/david/cva6/core/fpu/src/fpnew_opgroup_multifmt_slice.sv /home/david/cva6/core/fpu/src/fpnew_classifier.sv /home/david/cva6/core/fpu/src/fpnew_noncomp.sv /home/david/cva6/core/fpu/src/fpnew_cast_multi.sv /home/david/cva6/core/fpu/src/fpnew_opgroup_block.sv /home/david/cva6/core/fpu/src/fpnew_rounding.sv /home/david/cva6/core/fpu/src/fpnew_top.sv /home/david/cva6/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv /home/david/cva6/core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv /home/david/cva6/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv /home/david/cva6/core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv /home/david/cva6/core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv /home/david/cva6/core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv /home/david/cva6/core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv /home/david/cva6/core/frontend/frontend.sv /home/david/cva6/core/frontend/instr_scan.sv /home/david/cva6/core/frontend/instr_queue.sv /home/david/cva6/core/frontend/bht.sv /home/david/cva6/core/frontend/btb.sv /home/david/cva6/core/frontend/ras.sv /home/david/cva6/core/cache_subsystem/tag_cmp.sv /home/david/cva6/core/cache_subsystem/wt_dcache_ctrl.sv /home/david/cva6/core/cache_subsystem/amo_alu.sv /home/david/cva6/core/cache_subsystem/wt_axi_adapter.sv /home/david/cva6/core/cache_subsystem/std_nbdcache.sv /home/david/cva6/core/cache_subsystem/cache_ctrl.sv /home/david/cva6/core/cache_subsystem/miss_handler.sv /home/david/cva6/core/cache_subsystem/std_cache_subsystem.sv /home/david/cva6/core/cache_subsystem/wt_dcache_missunit.sv /home/david/cva6/core/cache_subsystem/cva6_icache.sv /home/david/cva6/core/cache_subsystem/wt_dcache_wbuffer.sv /home/david/cva6/core/cache_subsystem/wt_l15_adapter.sv /home/david/cva6/core/cache_subsystem/wt_dcache_mem.sv /home/david/cva6/core/cache_subsystem/wt_cache_subsystem.sv /home/david/cva6/core/cache_subsystem/wt_dcache.sv /home/david/cva6/core/cache_subsystem/cva6_icache_axi_wrapper.sv /home/david/cva6/corev_apu/bootrom/bootrom.sv /home/david/cva6/corev_apu/bootrom/dromajo_bootrom.sv /home/david/cva6/corev_apu/clint/axi_lite_interface.sv /home/david/cva6/corev_apu/clint/clint.sv /home/david/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv /home/david/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb.sv /home/david/cva6/corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv /home/david/cva6/corev_apu/fpga/src/apb_timer/apb_timer.sv /home/david/cva6/corev_apu/fpga/src/apb_timer/timer.sv /home/david/cva6/corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv /home/david/cva6/corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv /home/david/cva6/corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv /home/david/cva6/corev_apu/fpga/src/axi_slice/src/axi_slice.sv /home/david/cva6/corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv /home/david/cva6/corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv /home/david/cva6/corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv /home/david/cva6/corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv /home/david/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv /home/david/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv /home/david/cva6/corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv /home/david/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv /home/david/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv /home/david/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv /home/david/cva6/corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv /home/david/cva6/corev_apu/axi_mem_if/src/axi2mem.sv /home/david/cva6/core/pmp/src/pmp_entry.sv /home/david/cva6/core/pmp/src/pmp.sv /home/david/cva6/core/cvxif_example/cvxif_example_coprocessor.sv /home/david/cva6/core/cvxif_example/instr_decoder.sv /home/david/cva6/corev_apu/rv_plic/rtl/rv_plic_target.sv /home/david/cva6/corev_apu/rv_plic/rtl/rv_plic_gateway.sv /home/david/cva6/corev_apu/rv_plic/rtl/plic_regmap.sv /home/david/cva6/corev_apu/rv_plic/rtl/plic_top.sv /home/david/cva6/corev_apu/riscv-dbg/src/dmi_cdc.sv /home/david/cva6/corev_apu/riscv-dbg/src/dmi_jtag.sv /home/david/cva6/corev_apu/riscv-dbg/src/dmi_jtag_tap.sv /home/david/cva6/corev_apu/riscv-dbg/src/dm_csrs.sv /home/david/cva6/corev_apu/riscv-dbg/src/dm_mem.sv /home/david/cva6/corev_apu/riscv-dbg/src/dm_sba.sv /home/david/cva6/corev_apu/riscv-dbg/src/dm_top.sv /home/david/cva6/corev_apu/riscv-dbg/debug_rom/debug_rom.sv /home/david/cva6/corev_apu/register_interface/src/apb_to_reg.sv /home/david/cva6/corev_apu/axi/src/axi_multicut.sv /home/david/cva6/common/submodules/common_cells/src/deprecated/generic_fifo.sv /home/david/cva6/common/submodules/common_cells/src/deprecated/pulp_sync.sv /home/david/cva6/common/submodules/common_cells/src/deprecated/find_first_one.sv /home/david/cva6/common/submodules/common_cells/src/rstgen_bypass.sv /home/david/cva6/common/submodules/common_cells/src/rstgen.sv /home/david/cva6/common/submodules/common_cells/src/stream_mux.sv /home/david/cva6/common/submodules/common_cells/src/stream_demux.sv /home/david/cva6/common/submodules/common_cells/src/exp_backoff.sv /home/david/cva6/common/submodules/common_cells/src/addr_decode.sv /home/david/cva6/common/submodules/common_cells/src/stream_register.sv /home/david/cva6/corev_apu/axi/src/axi_cut.sv /home/david/cva6/corev_apu/axi/src/axi_join.sv /home/david/cva6/corev_apu/axi/src/axi_delayer.sv /home/david/cva6/corev_apu/axi/src/axi_to_axi_lite.sv /home/david/cva6/corev_apu/axi/src/axi_id_prepend.sv /home/david/cva6/corev_apu/axi/src/axi_atop_filter.sv /home/david/cva6/corev_apu/axi/src/axi_err_slv.sv /home/david/cva6/corev_apu/axi/src/axi_mux.sv /home/david/cva6/corev_apu/axi/src/axi_demux.sv /home/david/cva6/corev_apu/axi/src/axi_xbar.sv /home/david/cva6/corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv /home/david/cva6/common/submodules/common_cells/src/unread.sv /home/david/cva6/common/submodules/common_cells/src/sync.sv /home/david/cva6/common/submodules/common_cells/src/cdc_2phase.sv /home/david/cva6/common/submodules/common_cells/src/spill_register_flushable.sv /home/david/cva6/common/submodules/common_cells/src/spill_register.sv /home/david/cva6/common/submodules/common_cells/src/sync_wedge.sv /home/david/cva6/common/submodules/common_cells/src/edge_detect.sv /home/david/cva6/common/submodules/common_cells/src/stream_arbiter.sv /home/david/cva6/common/submodules/common_cells/src/stream_arbiter_flushable.sv /home/david/cva6/common/submodules/common_cells/src/deprecated/fifo_v1.sv /home/david/cva6/common/submodules/common_cells/src/deprecated/fifo_v2.sv /home/david/cva6/common/submodules/common_cells/src/fifo_v3.sv /home/david/cva6/common/submodules/common_cells/src/lzc.sv /home/david/cva6/common/submodules/common_cells/src/popcount.sv /home/david/cva6/common/submodules/common_cells/src/rr_arb_tree.sv /home/david/cva6/common/submodules/common_cells/src/deprecated/rrarbiter.sv /home/david/cva6/common/submodules/common_cells/src/stream_delay.sv /home/david/cva6/common/submodules/common_cells/src/lfsr.sv /home/david/cva6/common/submodules/common_cells/src/lfsr_8bit.sv /home/david/cva6/common/submodules/common_cells/src/lfsr_16bit.sv /home/david/cva6/common/submodules/common_cells/src/delta_counter.sv /home/david/cva6/common/submodules/common_cells/src/counter.sv /home/david/cva6/common/submodules/common_cells/src/shift_reg.sv /home/david/cva6/corev_apu/src/tech_cells_generic/src/pulp_clock_gating.sv /home/david/cva6/corev_apu/src/tech_cells_generic/src/cluster_clock_inverter.sv /home/david/cva6/corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv /home/david/cva6/corev_apu/tb/ariane_testharness.sv /home/david/cva6/corev_apu/tb/ariane_peripherals.sv /home/david/cva6/corev_apu/tb/rvfi_tracer.sv /home/david/cva6/corev_apu/tb/common/uart.sv /home/david/cva6/corev_apu/tb/common/SimDTM.sv /home/david/cva6/corev_apu/tb/common/SimJTAG.sv /home/david/cva6/core/mmu_sv39/tlb.sv /home/david/cva6/core/mmu_sv39/mmu.sv /home/david/cva6/core/mmu_sv39/ptw.sv  +incdir+common/submodules/common_cells/include/  +incdir+corev_apu/axi/include/  +incdir+corev_apu/register_interface/include/ -suppress 2583
** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
** Warning: /home/david/cva6/core/cvxif_fu.sv(43): (vlog-2696) Index 2 into array dimension 1 of 'rs' is out of bounds.
** Warning: /home/david/cva6/core/issue_read_operands.sv(457): (vlog-2696) Index 2 into array dimension 1 of 'rdata' is out of bounds.
** Warning: /home/david/cva6/core/cvxif_example/cvxif_example_coprocessor.sv(146): (vlog-2696) Index 2 into array dimension 1 of 'rs' is out of bounds.
** Warning: /home/david/cva6/core/cvxif_example/cvxif_example_coprocessor.sv(144): (vlog-2182) 'x_result_o[13]' might be read before written in always_comb or always @* block.
touch work/.build-srcs
mkdir -p work-dpi
g++ -shared -fPIC -std=c++0x -Bsymbolic -I/home/david/questasim/include -I/include -I/home/david/riscv-gnu-toolchain//include -I/home/david/riscv-gnu-toolchain//include  -std=c++11 -I../corev_apu/tb/dpi -O3 -c corev_apu/tb/dpi/SimDTM.cc -o work-dpi/SimDTM.o
mkdir -p work-dpi
g++ -shared -fPIC -std=c++0x -Bsymbolic -I/home/david/questasim/include -I/include -I/home/david/riscv-gnu-toolchain//include -I/home/david/riscv-gnu-toolchain//include  -std=c++11 -I../corev_apu/tb/dpi -O3 -c corev_apu/tb/dpi/elfloader.cc -o work-dpi/elfloader.o
mkdir -p work-dpi
g++ -shared -fPIC -std=c++0x -Bsymbolic -I/home/david/questasim/include -I/include -I/home/david/riscv-gnu-toolchain//include -I/home/david/riscv-gnu-toolchain//include  -std=c++11 -I../corev_apu/tb/dpi -O3 -c corev_apu/tb/dpi/msim_helper.cc -o work-dpi/msim_helper.o
mkdir -p work-dpi
g++ -shared -fPIC -std=c++0x -Bsymbolic -I/home/david/questasim/include -I/include -I/home/david/riscv-gnu-toolchain//include -I/home/david/riscv-gnu-toolchain//include  -std=c++11 -I../corev_apu/tb/dpi -O3 -c corev_apu/tb/dpi/remote_bitbang.cc -o work-dpi/remote_bitbang.o
mkdir -p work-dpi
g++ -shared -fPIC -std=c++0x -Bsymbolic -I/home/david/questasim/include -I/include -I/home/david/riscv-gnu-toolchain//include -I/home/david/riscv-gnu-toolchain//include  -std=c++11 -I../corev_apu/tb/dpi -O3 -c corev_apu/tb/dpi/SimJTAG.cc -o work-dpi/SimJTAG.o
# Compile top level
vlog +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+WT_DCACHE+RVFI_TRACE -timescale "1ns / 1ns" -sv /home/david/cva6/corev_apu/tb/ariane_tb.sv /home/david/cva6/corev_apu/tb/ariane_testharness.sv -work work  +incdir+common/submodules/common_cells/include/  +incdir+corev_apu/axi/include/  +incdir+corev_apu/register_interface/include/
** Warning: (vlog-13288) Multiple macros defined in +define+ command line switch.
** Note: (vlog-2286) /home/david/cva6/corev_apu/tb/ariane_tb.sv(20): Using implicit +incdir+/home/david/questasim/uvm-1.1d/../verilog_src/uvm-1.1d/src from import uvm_pkg
touch work/.build-tb
mkdir -p work-dpi
# Compile C-code and generate .so file
g++ -shared -m64 -o work-dpi/ariane_dpi.so work-dpi/SimDTM.o work-dpi/elfloader.o work-dpi/msim_helper.o work-dpi/remote_bitbang.o work-dpi/SimJTAG.o -L/home/david/riscv-gnu-toolchain//lib -L/home/david/riscv-gnu-toolchain//lib -Wl,-rpath,/home/david/riscv-gnu-toolchain//lib -Wl,-rpath,/home/david/riscv-gnu-toolchain//lib -lfesvr
# Optimize top level
vopt +cover=bcfst+/dut -incr -64 -nologo -quiet -suppress 13262 -permissive +define+WT_DCACHE+RVFI_TRACE -work work  ariane_tb -o ariane_tb_optimized +acc -check_synthesis
** Warning: (vopt-13288) Multiple macros defined in +define+ command line switch.
# vopt_stacktrace.vstf written
** Fatal: Unexpected signal: 11.
/home/david/cva6/core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv(1): Vopt Compiler exiting
make: *** [Makefile:344: build] Error 232

I have checked the warnings but the if conditions that check the value of NR_RGPR_PORTS seem ok. Any help on what the problem may be would be much appreciated. Thanks!

David

[christian-lanius]

Dear David, The same issue has also been raised in #800 I think. Unfortunately, this issue has not been resolved as of yet as far as I am aware. It seems related to the exact release of questasim you are using. I have tried the 2018 and 2020 version, where this issue occurs as well.

[davidmallasen]

The workaround of #800 works for me as well. However, without optimizations the simulation time is ~5x longer for a simple hello world. Thanks for sharing @christian-lanius ! I can't seem to pinpoint where the issue arises with the new patches (as it was working before commit 00236be3d8552f93a0bebda8f9820ec54b64a000), but if someone manages to find a solution it would be very helpful.

[christian-lanius]

The issue is related to the AXI interconnect I think. I have replaced the ariane core with a synthesized version and the same issue occurs, so it appears as if the actual core is not the culprit (at least not the coding style). I have looked at the axi repo and there I can run the test-benches for the interconnect just fine, so it must break somewhere in between, maybe the exact configuration of the interconnect. But I was unable to look too deeply into it.

[niwis]

This seems to be a vopt bug in newer versions of questasim. They struggle with parametric data types, which are used in several of our IPs. I get the same segfault for questasim version 2021.1, but not for 2020.3.

[christian-lanius]

I can confirm that this is questasim version related: Versions 10.7c generates a different error message, versions 2020.4 and 2021.3 generate the discussed segmentation fault. According to @niwis version 2020.3 works and I can confirm that version 2019.4 (which is the closest I have available) works as well. I suppose this can only be fixed moving forward by updating the readme with some info about this and the makefile with some error/warning message after checking the questasim version. Additionally, a bug report ought to be filled with Siemens/Mentor about this.

[christian-lanius]

So Europractice has made available a new version of Questasim (2022.4) and that version does indeed also fixes this issue! I mainly add this comment here for people trying to figure out which versions work. So I hope that this error does not reappear in the future with future versions of Questasim.

[MikeOpenHWGroup]

Hi @christian-lanius and @davidmallasen. It appears that this issue has been resolved. Please confirm, and if so close the issue, otherwise this issue will be closed by 2023-02-24. Thanks!

[davidmallasen]

I haven't been able to get my hands on the newer Questasim version, so I can't test it yet. However, if @christian-lanius tested version 2022.4 and it solves the issue, we can close it for now.