MMU: INSTR_ACCESS_FAULT triggered by PMP

[masgia]

In mmu.sv, line 247, there's a mixture of vaddr and PLEN, which causes a misalignment in tval icache_areq_o.fetch_exception = {riscv::INSTR_ACCESS_FAULT, {{riscv::XLEN-riscv::PLEN{1'b0}}, icache_areq_i.fetch_vaddr}, 1'b1}; Same for line 258 else icache_areq_o.fetch_exception = {riscv::INSTR_ACCESS_FAULT, {{riscv::XLEN-riscv::VLEN{1'b0}}, ptw_bad_paddr}, 1'b1};

[MikeOpenHWGroup]

Hi @zarubaf and @JeanRochCoulon. This is a report of a possible RTL bug that nobody has looked at. The code snip-it above is still in the CVA6 code. Please have a look.

[Jbalkind]

I think this was fixed or at least made consistent in #968

[JeanRochCoulon]

Indeed, it is solved ! Thanks for the fix ! @masgia to my mind you can close the issue