openhwgroup
[BUG] MInstret CSR is wrongly updated
Is there an existing CVA6 bug for this?
- [x] I have searched the existing bug issues
Bug Description
First, there is an old issue about it : #1997 But there are two bugs hidden in one.
minstreth and minstret are updated / incremented individually while they should be updated or incremented together.
RISC-V Specification
Unprivileged ISA: 20250508 | Privileged Architecture: 20250508 | SAIL Model: 20250709
Unpriviledge specification, page 51
Some CSRs, such as the instructions-retired counter, instret, may be modified as side effects of instruction execution. In these cases, if a CSR access instruction reads a CSR, it reads the value prior to the execution of the instruction. If a CSR access instruction writes such a CSR, the explicit write is done instead of the update from the side effect. In particular, a value written to instret by one instruction will be the value read by the following instruction.
Example scenario
Here are two different scenarios :
The first one simply accesses minstreth and minstret is wrongly updated.
The second one accesses minstret, and as its value is 0xffff_ffff, it is incremented to 0x1_0000_0000 which increments minstreth before being overwritten by csr_wdata.
branch: cv32a60x | targeted configuration: cv32a60x | targeted design: cva6_pipeline.sv
Product: Questa OneSpin Solutions App: Questa Processor App Tool's version: 2025.1
Hi @TeoBernier and @MikeOpenHWGroup. From what I can tell, this issue appears to be hardware-related rather than software, which falls outside my area of expertise. I believe someone with more cva6 architecture knowledge would be better suited to review and address this bug.
