[BUG] Tandem verification with generated tests triggers occasional differences on SLT/SLTI result values

[zchamski]

Is there an existing CVA6 bug for this?

• [x] I have searched the existing bug issues

Bug Description

Systematic verification of CV32A65X with updated CV-X-IF support (see issue #2626) using DV-generated semi-random tests occasionally triggers a discrepancy on SLT and SLTI instruction results.

Example : with a0 = 0x86ccb60b, the instruction slti s0, a0, -2018 clears s0 in Spike and sets it in RTL. The RTL seems to behave correctly here, so the problem is probably in Spike. However, visual inspection of Spike implementation of SLTI provided no direct clues regarding the cause of the observed behavior.

Due to the (semi)random nature of the tests that trigger this bevahior, unit testing will be necessary in order to isolate the problem.