[BUG] CVA6 core throw `Store Address Misaligned` while address for `Load-Reserved` is misaligned

[riscv914]

Is there an existing CVA6 bug for this?

• [X] I have searched the existing bug issues

Bug Description

When executing Load-Reserved instructions (e.g. LR.D) with a misaligned address, CVA6 core throw Store Address Misaligned while it should throw Load Address Misaligned.

To reproduce, execute following instruction:

int main(void){
    // Load an address in ra which is not 8-bytes aligned e.g. 0x0000000080001054
    asm volatile ("lr.d    s1, (ra)");
    // Exception @ Cause: Store Address Misaligned,
}

However, if you execute same code on Spike you will get trap_load_address_misaligned exception.

- Spike version: `1.1.1-dev`
- version: `CVA6 commit: 7435cb310ee98c246edd15d00ec236ad2c6ff490`
- OS: `CentOS Linux release 7.9.2009 kernel: 5.15.0-78-generic`
- Simulator: `VCS_2023`

[JeanRochCoulon]

Thank you @riscv914 for this input.