cva6 Define Memory Access Type

Is there an existing CVA6 bug for this?

[X] I have searched the existing bug issues

Bug Description

The type of memory access is information we need to check other CVA6 components. I'd like to know if there's a way, from the current AXI interface, to provide information on whether we're fetching or not.

Jul 29 '24 15:07 AEzzejjari

If I understand, the read and write information is present, but the fetch is not present on AXI.

On another hand, what is the status of OBI ?

Jul 30 '24 07:07 JeanRochCoulon

Hello, I'm not sure to understand the question. Was the original question @AEzzejjari if there is a way to see if a given AXI request is an instruction cache miss ?

Regarding OBI, I need to make a meeting with Akiho to see how is she progressing. I will let you know as soon as I have some news.

Jul 30 '24 08:07 cfuguet

To me, @AEzzejjari is looking for an information from AXI bus to know whether an access is a fetch or not. Can you confirm @AEzzejjari ?

Jul 31 '24 05:07 JeanRochCoulon

Ok, if that is the question, then yes, there is a specific AXI ID for Icache miss transactions.

core/cache_subsystem/cva6_hpdcache_subsystem.sv:148:localparam int ICACHE_RDTXID = 1 << (CVA6Cfg.MEM_TID_WIDTH - 1);

Jul 31 '24 05:07 cfuguet

👋 Hi there!