[BUG][cv32a65x] Zicntr support: conflicting information between documentation and RTL

[zchamski]

Is there an existing CVA6 bug for this?

• [X] I have searched the existing bug issues

Bug Description

The unprivileged ISA specification of the CV32A65X describes the Zicntr extension as if it were fully supported. However, the RTL setting in https://github.com/openhwgroup/cva6/blob/master/core/include/cv32a65x_config_pkg.sv in commit 4ff16f9 says RVZicntr: bit'(0) suggesting that this extension is not supported.