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scoreboard.sv [BUG] : RTL assertion failed

Open AyoubJalali opened this issue 1 year ago • 7 comments

Is there an existing CVA6 bug for this?

  • [X] I have searched the existing bug issues

Bug Description

For now I don't know the real cause of this issue, but I wanna file it in github. An assertion is failed in CVA6 scoreboard.sv : image

to regenerate the problem : python3 cva6.py --testlist=cva6_base_testlist.yaml --test riscv_unaligned_load_store_test --iss_yaml cva6.yaml --target cv32a65x -cs ../env/corev-dv/target/rv32imcb/ --mabi ilp32 --isa rv32imc --isa_extension="zba,zbb,zbc,zbs,zcb" --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike --priv=m -i 1 --iss_timeout 300 --seed 888640121

CVA6 version : 8c709767599a12acd7c02976a42cc3dcc9f4604e core-v-verif version : 66cd091b84489d855dc0542b0d7f8337e82e2ef3

AyoubJalali avatar Jul 22 '24 09:07 AyoubJalali

According to the simulation waveforms, there is an issue in the load_unit. A request is made with transaction id 6, then it returns with transaction id 7 instead of 6.

cathales avatar Jul 22 '24 13:07 cathales

@cathales We are cleaning the "Github Issues". What is the status of this issue ?

JeanRochCoulon avatar Jan 02 '25 16:01 JeanRochCoulon

I think @yanicasa is more aware about what happens in the load_unit than I am.

cathales avatar Jan 06 '25 08:01 cathales

On the future CV32A65X branch, with the OBI buses, the logic has been updated a lot, there is more checking on common exceptions from mmu/Missalign/pmp which go back to the load/store/amo to be sure not to catch an exception an exception intended for an other unit. That could be the root cause of this issue. Since these modifications we have not reproduced the problem (even with the same simulation seed), the test is stable on the pipelines

The label can be updated notCV32A65X

yanicasa avatar Jan 24 '25 15:01 yanicasa

Hello,

I just observed this assertion failing as well while running smoke-gen_test.sh for cv32a65x. What surprises me a little is even if assertion fails the test is not signaled as failed. It feels like as if only mismatched between spike and simulation are considered as failure ? Is it something that you have observed or I need to do may be more manipulation to get the exact result of the run ?

Thanks and Regards Tanuj

khandelwaltanuj avatar Feb 05 '25 08:02 khandelwaltanuj

I think this issue is already reported in #1624 If it is not the case, please elaborate.

JeanRochCoulon avatar Feb 05 '25 14:02 JeanRochCoulon

Yes this is the case

Thanks

khandelwaltanuj avatar Feb 06 '25 14:02 khandelwaltanuj