[BUG] uvme_exception_covg and uvme_illegal_instr_covg not compliant LRM

[CoralieAllioux]

Is there an existing CVA6 bug for this?

• [X] I have searched the existing bug issues

Bug Description

We are currently porting the verification to be compliant with Cadence Xcelium simulator. The objective is to use the current verification flow and adapt it, to add the Cadence simulator. This issue concerns the cva6/verif/env/uvme/cov/uvme_exception_covg.sv and cva6/verif/env/uvme/cov/uvme_illegal_instr_covg.sv.

For uvme_exception_covg.sv, the issue is coming from the following code: bins BREAKPOINT_EXC_RAISED = (NO_EXCEPTION => BREAKPOINT => NO_EXCEPTION); A bin name cannot be used inside a bin with a transition, xcelium does not allow it.

For uvme_illegal_instr_covg.sv, the issue is about the covergroup cg_illegal_i: the variable legal_i_opcode is "Illegal operand for covergroup expression [19.5(SVLRM-2012)]". The usage of legal_i_opcode in this context is not then not compliant with the LRM.

From now, we would like to get a solution to make work those covergroups for xcelium, which we still not manage to fix: we need a better understanding of the purpose of those lines. We already discussed a bit with @AyoubJalali. Could you please better explain what you meant to achieve? In order to better look at potential solutions. Thank you!

[AyoubJalali]

For the first issue, it's fix on master For the legal_i_opcode my intend is to sample my bins only if we have the right opcode or the wrong opcode, the legal_i_opcode is define in https://github.com/openhwgroup/cva6/blob/0721ebb609044a4504be2d99751a0328856575bb/verif/env/uvme/uvme_cva6_pkg.sv#L63