cva6_icache: Allow one outstanding killed miss

[colluca]

This PR fixes issue https://github.com/openhwgroup/cva6/issues/1785, implementing the same performance enhancement proposed in PR https://github.com/openhwgroup/cva6/pull/1497.

Compared to the latter, it fixes a problematic corner case, which was likely the cause of the regression errors observed.

Said corner case occurred when the following two conditions were met:

• We incur in a second speculated instruction cache miss during a previous outstanding killed miss
• Upon branch resolution, the second refill is killed

The second miss brought the I$ in the MISS state, where it was correctly waiting for the previous outstanding killed miss to complete. However, the kill_s2 signal was not being used here, effectively ignoring the branch resolution outcome.

This PR fixes this behaviour by counting the number of outstanding killed miss requests. Max one killed refill can be handled in parallel with other requests. Thus, as the second miss is killed, we stall the cache in the WAIT_MISS state, as originally was the case upon the first killed miss, so long as we don't again have a single outstanding miss.

I ran the smoke-tests locally, as described in the repo's README, and it seems to pass, but I'm not sure I'm doing this correctly.

[github-actions[bot]]

:x: failed run, report available here.

[JeanRochCoulon]

@colluca Nice to see you continue the work on this PR ! I committed the expected Coremark value in your PR, I hope it is ok for you

[github-actions[bot]]

:x: failed run, report available here.

[JeanRochCoulon]

Aie, when FPGA boot is fail, it is a mess. @Gchauvon would you have a root cause input ?

[github-actions[bot]]

:x: failed run, report available here.

[github-actions[bot]]

👋 Hi there!

This pull request seems inactive. Need more help or have updates? Feel free to let us know. If there are no updates within the next few days, we'll go ahead and close this PR. 😊