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openhwgroup
[BUG] : MISA value change
Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
Bug Description
Hello, when trying to write to misa csr (random value), that value change, the operation clear the C extension bit, then Spike raise an exception on every compressed instruction (that's normal), but the MISA should have a fix value (reset value) identifying the supported extensions.
to reproduce the Bug: source ./verif/sim/setup-env.sh python3 cva6.py --testlist=../tests/testlist_csr_embedded.yaml --test csr_test --iss_yaml cva6.yaml --target cv32a6_embedded --iss=spike
Spike code assumes that standard extension bits MAFDQCHV of the Extensions field in misa CSR are writable (see riscv/csrs.cc:622). On the other hand, the privileged spec (Version 20211203, page 16) states that:
The Extensions field is a WARL field that can contain writable bits where the implementation allows the supported ISA to be modified.
Since in CVA6 the ISA is non-modifiable, the set of writable misa.Extensions bits should be reduced to empty using a Spike configuration parameter.
Hey @AyoubJalali. I think this has been resolved by @MarioOpenHWGroup. You can check it with the test added with this PR : https://github.com/openhwgroup/cva6/pull/1976 . It basically tries to write in misa and disable compressed instructions, then to execute compressed instructions. If this is ok for you I think this issue can be closed.
