Immediate assertions in the CVA6 RTL

[MikeOpenHWGroup]

Is there an existing CVA6 bug for this?

• [X] I have searched the existing bug issues

Bug Description

This issue is motivated by #1619.

A quick grep of the CVA6 RTL reveals approximately 50 assert statements of the form assert (expression);. These are called "immediate assertions" in the SystemVerilog LRM. Immediate assertions without an else clause are dangerous because they will only emit a simulator-specific message to stdout, without interacting with the simulator or the testbench. That is, once the assertion fires and the message is written to stdout, there is no further record of the assertion, so it is not possible for the testbench to know that the assertion happened, and bugs can be missed.

For that reason there should be an else clause for all assertions:

assert (expression)
  else `uvm_error("<Identifier>", "Useful (?) error message")

In non-UVM environments. the uvm_error() could be replaced with either $error() or $fatal(). In these cases, the script that launches the simulation must post-process the logfile to check for these messages. This is not considered ideal since it is easy for the error message in the logfile to be missed.

To resolve this Issue I propose the following:

• Create a "cvv_error()" macro that will emit either a uvm_error() for UVM simulations or $fatal() for non-UVM sims.
• Update all immediate assertions to add an else clause as follows:

assert(expression)
  else `cvv_error("<Identifier>", "Useful (?) error message")