Dual issue

[JeanRochCoulon]

What The goal is to provide a faster version of CVA6, with an opt-in configuration option to enable dual-issue.

Howto The new configuration parameter will impact the fetch width (32 or 64 bits, in the frontend); the number of issue ports (single or dual issue, issue stage) and add an ALU (EX stage).

Current status CVA6 currently is single issue. Some places in the frontend are generic but not all.

Risks The implementation could not provide as much performance as we hope; or require too much power, area or timing.

Prerequisites None

KPI The development is split in three steps: fetch, issue and execute. Thanks to a model, we have an expected performance (CoreMark/MHz) for each step. The progress indicator is the step done (functional single- and dual-issue, no impact on single-issue and expected performance on dual-issue).

Description of done CVA6 should be able to issue up to 2 instruction each cycle and reach the expected performance goal.

[jay1sung]

Hello,

It looks like CVA6 is capable of Dual Issue. When are you expecting to release RTL for Dual Issue of CVA6?

Thanks,

Jay

[JeanRochCoulon]

Hi Jay By the end of the year, the dual issue will be functional. Then verification could start.. Cheers

[jay1sung]

You said "The progress indicator is the step done (functional single- and dual-issue, no impact on single-issue and expected performance on dual-issue)." So I understood that you already completed the function/performance check. You mentioned a model that is software language not RTL?

Thanks,

Jay

[JeanRochCoulon]

That is a python model which (tries to) estimate the performance gain. Regards

[jin8495]

Hi, @JeanRochCoulon. I am interested in the dual issue feature. But this Github issue has had no progress since October. I'm just wondering how things are going.

Thank you.

[cathales]

@jin8495 We have a working version of superscalar CVA6 and we will add new features to improve performance further.

Superscalar CVA6 will be released step-by-step (there are many versioning conflicts since development started!) in the following months; and the release will be completed by the end of the year.

FYI It has been presented during the last CVA6 verification workshop and the slides are available on OpenHW Group Mattermost. A presentation will be made at CF24-OSHW.

@jay1sung The model is now available on GitHub: https://github.com/ThalesSiliconSecurity/cva6-perf-model

[jin8495]

@cathales Thank you for the information. That is really what I want. 😄

[cathales]

Update: ETA is July the 5th

Cc @jin8495

[cathales]

Notes from https://github.com/openhwgroup/cva6/pull/2047 for parametrization of superscalar (feel free to discuss these points)

• Need two options bit SuperscalarEn and int unsigned PIP_WIDTH
• NrCommitPorts can be replaced by PIP_WIDTH
• Try to make Verilator understand that [1] is never used unless SuperscalarEn
• core/frontend/instr_queue.sv Update NID and its comment