Spike Configuration for CVA6 CSR Verification

[spidugu444]

Hi, while verifying access modes for PMPADDR CSR I am facing issues on spike configuration as mentioned below.

As CVA6 core has a granularity of 8 bytes that bit-0 of the PMPADDRCSR has been hardcoded to 0, After making bit-0 to zero on RTL end test is running fine but on spike end default reset value of PMPADDR0 CSR is reading as 0xFFFFFFFF.

for PMPADDR1-PMPADDR7 CSRs after making bit-0 to zero, on RTL end test is working fine, so to make test working on spike end we need to configure PMPADDR CSRs bit-0 to zero.

could anyone please help me in configuring spike to resolve above issues.

Thanks, Sai Krishna

[ASintzoff]

Related to task https://github.com/openhwgroup/cva6/issues/1403

[zchamski]

The reset value of PMPADDR0 can now be set in Spike using the parameter /top/cores/pmpaddr0 (or its per-core version /top/core/.../pmpaddr0). Testing has yet to be done.

[zchamski]

However, the root cause of the 0xffffffff value appears to be the mismatch of PMP granularity (8 in RTL, 4 in Spike unless overridden in the device tree), see https://github.com/openhwgroup/cva6/issues/1403#issuecomment-1851969714.

[zchamski]

However, the root cause of the 0xffffffff value appears to be the mismatch of PMP granularity (8 in RTL, 4 in Spike unless overridden in the device tree), see #1403 (comment).

Upstream Spike finally supports PMP granularity: the corresponding variable and cmdline option were introduced in Nov 2023 in commit riscv-software-src/riscv-isa-sim@5bdb9d4d7. This means that an upgrade of "our" vendiorized Spike from upstream will provide a solution for the root cause of the incorrect value in PMPADDR0.

[MarioOpenHWGroup]

I think this issue is solved as the core was hardcoding the LSB to 0 even if the region was in OFF. This was solved as can be seen in the RTL https://github.com/openhwgroup/cva6/blob/master/core/csr_regfile.sv#L796

[zchamski]

fixed, should be closed.

[valentinThomazic]

Fixed, closing the issue.