cva5
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Preliminary OS support
This PR includes initial changes that will be necessary to run an operating system on CVA5 in the future. In addition to clarity and QoL changes, this primarily includes:
- Full support for the 20240411 RISC-V privileged architecture (previously a draft spec from ~2017-2019 was mostly supported)
- New separate TLB's for instructions and data
- Support for Sv32 virtual memory
- Many significant bugfixes for interrupt and exception handling (can close #19)
- Support for the RISC-V atomic extension (can close #21)
- Simulation support for the latest version of Verilator