cv32e41p
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openhwgroup
Remove PULP
PULP conflicts with Zce instructions, and increase the complexity of the core while not being used, thus it should be removed.
Hello @abukharmeh - we initially agreed to keep the PULP extensions, that's why we have the "P" in the name of this core. Without the PULP extensions, this core would be pretty much a subset of the existing CV32E40X core - Although the verification of the functionality of these instructions is out of the scope of this specific project, following projects may be interested in having the PULP ISA verified - especially after the CV32E40P project 2 (aka v2) completion, that aims to verify at TRL5 the PULP instructions.
May I ask you to report which instructions collide with the Zce?
As you may know, the PULP instructions will be relocated following the scheme proposed here: https://github.com/openhwgroup/cv32e40p/issues/452, i.e. using only CUSTOM opcodes.
If they still collide (i.e., the Zce overlaps with the CUSTOM opcodes), we can decide to remove in the future those PULP instructions that indeed collide and keep the others. In that case, we can open an issue saying which instructions collide with the new proposed encoding so that we can remove them in the future.
For this project, let's just assume that the PULP parameter is always set to 0 (adding an assert pointing to this discussion for example) - but let's not removed them.
Let's keep this issue open until both this https://github.com/openhwgroup/cv32e40p/issues/452 and your analysis have been completed.
The final version of Zce will only contain 16-bit encodings - so the conflict will be resolved. See this tagged release: https://github.com/riscv/riscv-code-size-reduction/releases/tag/V0.70.1-TOOLCHAIN-DEV Currently we're waiting for the toolchain to be updated to this version, before moving the core forwards.
