Blocking assignment in an always_latch block

[MikeOpenHWGroup]

As discussed in #753, cv32e40p_register_file_latch.sv uses a blocking assignment in an always_latch block, and I believe that is not compliant with the LRM (clause 9.2.2.3 of 1800-2017).

It is not clear to me that this has caused any functional issues in either RTL or gate-sims.

[davideschiavone]

as cv32e40p supports at TRL5 only the FF-based RF I added the WAIVED label, but still to be fixed in my opinion. @pascalgouedo ? what do you think? will you use the latch-based RF in your project?

[pascalgouedo]

Hi, We are not using latch-based design. But in my opinion we should correct it and cv32e40p_sim_clock_gate as well to totally get rid of further problems or remarks.

Even if as said by @MikeOpenHWGroup Verilator is not an OpenHW target, it is heavily used by Embecosm to verify all new v2 features for next GCC toolchain.

Cheers, Pascal.

[davideschiavone]

the clock gate file should be correct (it uses <= and not =)

For Verilator we can always apply a compile time waiver

[gullahmed1251]

I also faced the same error. I just replaced the <= with < and now it's compiling without any error.

[MikeOpenHWGroup]

Hi @gullahmed1251, I hope you meant to say "I just replaced the <= with =".

[gullahmed1251]

Yeah, you are right. I just noticed it.

[MikeOpenHWGroup]

Hi @davideschiavone and @pascalgouedo, what is the status of this issue. I believe it was agreed to fix it, but there hasn't been a resolution and the "waived" label was still applied.

I have removed the label and assigned the issue to both of you.