Oliver O'Halloran

Parsing the EEH register dump: ``` ==== PHB Register dump found ==== [ 73.061847781,3] PHB#0033[8:3]: PCI FIR=2000000000000000 NEST FIR = 0000800000000000: 16 - PFIR_freeze PCI FIR = 2000000000000000: 2 -...

Thanks for the logs. I noticed there's some odd stuff in there: ``` [ 73.390875079,7] PHB#0033[8:3]: 100 CFG8 Wr 18=00000001 # write the default bus numbers [ 73.390876229,7] PHB#0033[8:3]: 100...

That log says that PCI probing is pretty much instant: ``` [ 4.072493625,5] PCI: Probing slots... ... [ 4.118325244,5] PCI Summary: ``` The time consuming part is resetting each PHB...

So I was looking at this today and we might be able to make it a bit faster. Currently the PHB3 model always reports that there is in-band presence since...

@legoater Sure, it won't fix the problem here, but it makes the model a little better and shouldn't break anything. The PHB4 model has the same issue too.

I'm not really sure how we're supposed to fix this since we don't really parse the guard partition at all in skiboot. Suppose we could force a full re-IPL if...

SCOM addresses are just offsets into the XSCOM MMIO area. The SCOMs themselves are big endian MMIO registers so we use in_be64() and out_be64() to access them.

More or less. Historically SCOMs were accessed from outside the chip via a address/data register pair and the "scom address" needs to be translated from a register number to an...

From memory this was fixed by falling back to training at Gen1 speeds. Can we close this @madscientist159?

@debmc any updates on this?