Olof Kindgren

This looks very strange. I will need to investigate

Verilator 3.918 is too old unfortunately. I see now that the instructions are out of date. I don't remember right now which is the minimum version that works, but I'm...

Thanks @JanMatCodasip, That sums it up quite well. I guess the other half of the answer is _why_ we do it like this. On the Nexys A7 board, the dedicated...

That part about the missing FTDI connections rang a bell so I did some research and yep, [been through this before](https://twitter.com/OlofKindgren/status/1144176833040134144). :) So to sum it up, it's a good...

@MatthewMFLai Is there any particular reason you need a separate JTAG cable? SweRVolf supports both JTAG, UART and power over the same USB connection and this is the normal way...

I plan to support EH2 eventually, but it is not prioritized right now

It's hard to say right away what went wrong here. Synthesis failed for some reason. Could you please check for errors in `build/swervolf_0.7.4/basys3-vivado/swervolf_0.7.4.runs/synth_1/runme.log` That would give me a better idea...

Lots of warnings is unfortunately expected but there should had been an error for to make the build stop. I do have another theory though. Looking at your initial report...

Hmm.. it looks like some propblems with `/` and `\`. I'm not sure how to fix this and I don't use cygwin myself. Help from any Cygwin users would be...

It looks like you don't have vivado in your path. Try adding it to your path and see if that fixes the problem