Oliver Bründler

Sin() mismatch

3

**Description** The results of my simulations in Modelsim and GHDL do not match. I tracked down the issue a bit and found out that the result of the coefficient calculation...

hdl parse not working for parsing an entity

1

I tried hdlparse for parsing a small entity. The entity is known to be correct (used in many projects and working fine for synthesis and simulation). However, hdlparse just returns...

I think the debouncer should implement debouncing per bit. At the moment it is implemented to only forward data if all bits are stable. Hence if one bit in dat_i...

The timing or o_reg_rd is wrong for fixed burst transfers. If I connect a FIFO to one register address and I read a new value on every o_reg_rd='1', the first...

Narrow burst handling (ArSize/AwSize < 32resp 64 bits) is implemented partially (for wrapping bursts ArSize is considred) but the implementation is incomplete. Handling narrow bursts is not implemented in most...

When RReady toggles instead of being constantly high, backpressure is not handled correctly and wrong data is returned. This is a conceptual problem. To correctly handle backpressure, a FIFO on...

How to enforce snail_case for Function/Procedure arguments?

6

Is it possible to enforce snail_case for VC procedure arguments? I configured them for "case: lower" - but this does not report errors if I name an argument in camelCase...

Alignment incorrect for range declarations of unconstrained record elements spread over multiple lines

3

**Environment** Ubuntu 20.04 **Describe the bug** Range declarations for unconstrained record elements are off by one column if spread over multiple lines (otherwise VSG does report errors). Can this be...

Indentation wrong for Functions/Procedures Without Arguments

3

**Environment** Ubuntu 20.04 **Describe the bug** VSG seems unable to handle procedure without arguments - indentation was messed up in this case. I worked around this by adding an ugly...

Report warnings as errors + How to update configuration YAML for newer versions

3

Hi Jeremiah, I am using VSG to lint my open-source FPGA standard library [Open Logic](https://github.com/open-logic/open-logic). I have two questions: 1. Is there a way to report warnings as errors? For...