Olexa Bilaniuk

@travisdowns Yessir, will get down to writing it. This Github repo would probably be the best place to discuss it. In the README or in the Wiki page. I don't...

@travisdowns There's the beginnings of a `README.md` in the repo now, though much remains unsaid, especially about the kernel code.

@travisdowns They are defined [here](https://github.com/obilaniu/libpfc/blob/master/include/libpfc.h#L71). `pfcRemoveBias()` automatically computes the costs for the current counter configuration. In particular, both sequences cost _precisely_ the same (Assuming `add/sub` with memory operands cost the...

@travisdowns Well, technically, 7 counters (3 fixed, 4 general-purpose). It would be possible to read a subset by hacking the inline asm macros, but I wanted to avoid branches in...

@travisdowns Other thing to note, certain performance events can only be counted on certain counters (Some L1/L2 events can only be counted in GP1, for instance). I've no idea why.

@duttasankha `libpfc` certainly can't program the uncore PMU (including its CB0 counters). You might be able to program the `llc.miss` counter, however. Start from and modify my [`pfcdemo.c`](https://github.com/obilaniu/libpfc/blob/master/src/pfcdemo.c#L128), but use...

@travisdowns The answer is "Yes"! The code that supports it is [here](https://github.com/obilaniu/libpfc/blob/master/src/libpfc.c#L602-L619). You just need to add `:a` to the config string. The default is implicitly `:u`. **EDIT** and for...

I did some of the more tedious work related to supporting a new MSR, and exposed it for reading, though not writing (because `/sys/module/pfc/msr` is read-only for now). I suppose...

Yes, this might be valuable... The reason I always read 3+4 counters in a specific order and with no dynamic customization was to maximize the predictability of the `PFC_START/PFC_END` macros...

@travisdowns I have not really tried to access the MSRs using the `msr` LKM. I suppose I could. I had written my own LKM in the expectation of setting everything...