sdram-fpga
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nullobject
A FPGA core for a simple SDRAM controller.
I have added support for a data mask (byteenable). It was testet on a DE0-nano board with the neorv32 project. I am not sure if I must add the mask...
Currently the `sdram_dqmh` and `sdram_dqml` signals are hard-wired to zero. I assume that these two signals can be used for implementing "byte select" during write operations. For my application (a...
Write an address to the **addr bus** and a **value to the data bus.** Request a write operation by asserting the we and req signals. Wait for the ack signal...
There are a few changes that will allow compatibility with SDRAM memory on the CYC1000 FPGA board. I tested your SDRAM controller in HW using my design https://github.com/jakubcabal/sdram-tester-fpga. Thanks
I only have 16x8 parts available from old dual bank ram modules. I'd very much like to recycle old hardware instead of buying new parts. Is it possible? Cheers!
parametrized DQM byte select size, there are 32-bit 64MB chips with 4 DQM.
HI For video framebuffer to optimize RAM bandwidth and allow higher display resolution, some sequential read bursts of 1-2K from RAM would mean much. If you have some plans or...
Hi, to save more than the default numbers of words (BURST_LENGTH == 2) i did the following modification @ process "latch_sdram_data" signal word_cnt_int : natural range 0 to BURST_LENGTH-1; if...
the code here im trying to use this, but i have no idea where to start i've added the single file to project file. but i have a different TOP...
