Why add data again in the second burst write?

[sixstringsdev]

Write an address to the addr bus and a value to the data bus. Request a write operation by asserting the we and req signals. Wait for the ack signal to be asserted. This means that the write request has been acknowledged, and a write operation has begun. Write another address to the addr bus and a value to the data bus. Wait for ack signal to be asserted. This means that the second write request has been acknowledged, and a write operation has begun. Deassert the we and req signals when we're done making requests.

Hi, Josh thanks for this controller. I have a question for the bold lines. Since I understand the first step is to set the address(22 in my case 2BANK-12ROW-8COLUMN) and the data bus(32). Since it's in 2 burst mode, the first 16 bits are written in the address, once ack is rised it says that I need to set again a new address and ¿new data? what about the 16 bits left? Can u help me in that?

Thanks for the answer!