netlistsvg
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Published
20 hours ago •
nturley
nturley
draws an SVG schematic from a JSON netlist
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out.svg was generated like this: netlistsvg synth.json and synth.json was generated using yosys write_json after standard synthesis from a verilog file. $ xdot gen_yosys/out.svg Error: : syntax error in line...
Hi, can it be that Tri-State Logic is not supported? I am implementing a shared bus I skimmed through the generated json file and have following block: "$ternary$top.v:302$4": { "hide_name":...
