Nick Gasson

> 1. The coverage is generated "per-file" instead of "per-instance". IMHO per-instance is much more important. "Per-file" can be generated as sub-set of per-instance. Do I understand it correctly that...

> 1. Multithreaded simulation - How do you want to approach this? Scheduling events from event queue in parallel? Or partitioning the design based on hierarchy into "separately" executed simulations...

> > 1. For T_IF and T_CASE, I would add a separate coverage tag for each condition, for IFs also for "implicit else". I find "implicit else" useful since it...

> Btw. I have seen that "simp" pass converts all "VHDL specific" parallel statements to sequential statements. So is it safe to assume that T_IF, T_CASE, T_FOR, T_WHILE are the...

> > Would it be OK, if I replaced default naming of sequential and parallel statements with an incrementing counter per hierarchical scope? In that case, each statement can be...

> exclude branch .B0.TRUE > exclude branch .B0.FALSE Is that syntax with B0, etc. for individual conditions taken from a commercial simulator like ModelSim? TBH I never used that feature...

> > Do you maybe have some suggestion where to look here? How could I emit code during signal assignment, which would cause that once a signal / port value...

Thanks for the interest in this project! I'd definitely like to add PSL support in the future. Recently I've been focussing on adding missing -2008 features which will include PSL...

I've thought about this before and I think it would be a useful feature. But right now I'm focussing on improving VHDL-2008 support and maybe basic Verilog after that.

Thanks for that example: I haven't used VHPI much before. Out of curiosity, which commercial simulators are you using to test this? Last time I checked Modelsim didn't support VHPI.