nicdes

Questa Sim 2022.4_2 changes default bit ordering in unconstrained arrays. Test tb_uart_lib.tb_uart_rx.test_receives_one_byte broken.

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Updating questasim from 2020.1_1 to 2022.4_2 breakes the test 'tb_uart_lib.tb_uart_rx.test_receives_one_byte': ``` # 73810000 ps - check - ERROR - Got 1110_1110 (238). Expected 0111_0111 (119). ``` And I expect many...

Implementation of the parity bit (none, even, odd, mark, space) in the uart VCs. - Adds a parity_mode in the uart_master_t and uart_slave_t records [(uart_pkg.vhd).](https://github.com/nicdes/vunit/blob/484d2d11537363899fcdddf47daf98886d7792e0/vunit/vhdl/verification_components/src/uart_pkg.vhd#L20) - [uart_master.vhd](https://github.com/nicdes/vunit/blob/484d2d11537363899fcdddf47daf98886d7792e0/vunit/vhdl/verification_components/src/uart_master.vhd#L49) sends the parity...

Parity bit. The constructors accept a parity argument with an enum specifying the parity mode: none, even, odd, mark, or space. Note: this includes PR https://github.com/alexforencich/cocotbext-uart/pull/3, as I needed those...

Thanks for the code! Just a couple of things: - UartSource write() is not blocking but calls write_nowait() - The description of idle() in the README.md should have 'and' instead...