navaneeth-cirel

Endianness in WishboneDMAReader

2

Hi, Shouldn't this be opposite ? https://github.com/enjoy-digital/litex/blob/78c1751c4781ffe156128748810ee4af85fee058/litex/soc/cores/dma.py#L19-L20 Just to try this out I used the `WishboneDMAReader` in a module of my SoC (with vexriscv) simulation to read a word from...

Silicon validation results

6

Hi, Are there any test results from the silicon which was taped out for core-v-mcu? Thanks

Hi, The code generated of FSM does not capture the `FSM()` object name (similar to `Signal()`), due to this the traces in VCD file has signal names like fsm0, fsm1...

Cycle accurate simulation

2

Is it possible to perform cycle accurate simulation using the inbuilt simulator in migen?