Nathaniel Navarro

This is amazing! I'm implementing changes to code generation now. Sorry if this question has an obvious answer, I looked around but couldn't find one. Thought it might save time...

After discussing with @rachitnigam, the goal is to write a [cocotb](https://github.com/cocotb/cocotb) [AXI test harness](https://github.com/alexforencich/cocotbext-axi) that would use Icarus Verilog (Verilator is only supported on version 4.106).

Currently changing this to only test a single calyx program: vectorized-add. I think one test is better than no test, and runt behaves strangely when supplied more than one [directory](https://github.com/cucapra/calyx/pull/1153/files#diff-4de5114f2b8940b402eab836491023d894ceb8854235d1dda559364646b82aeaR293)....

So (finally!) had some time to fix this! Apologies for taking so long. I believe the most recent push should fix the one-computation-kernel issue

> @nathanielnrn seems like the tests are failing? Has to do with the `AxBurst` ports I added to make cocotb happy, probably should have made another branch for this. Updated...

Latest commit makes the `toplevel.v` and `main.sv` we use for `cocotb` be dynamically generated as expected. However, the runt tests we have aren't passing due to differences in a newline...

EDIT: A working reproducible example is listed in another comment below --- ~~So I _thought_ something like this would reproduce the bug, where we drive `write_en` in the writer component...

Ok found a calyx program that reproduces these results. It should be noted that this only happens in `icarus-verilog` simulation, which I believe is because `verilator` treats `x` as zero-ish...

Bumping this because this might be able to be closed as runt now contains tests that emulates AXI-wrapped hardware using cocotb on our vectorized-add and dot-product examples. The runt tests...

> @nathanielnrn Seems like you might've committed a bunch of formatting changes. Can you separate them into a different PR or remove them entirely? Once done, I can re-review. Sorry...