narutozxp
narutozxp
How can I use the routing resource map for placement and routing? Even though I read in the wiring resource diagram, VPR still requires me to provide the xml description...
The VPR in openfpga does not seem to support visualization, so can we use the original VPR in the VTR to generate the placement and routing results, as well as...
It seems that grid_layouts.size() is always larger than 1, even if my architecture has just one layer. Therefore, the following code will result in segment fault. https://github.com/verilog-to-routing/vtr-verilog-to-routing/blob/17a816ac90a21ca197cd14b783f36236cc214f61/libs/libarchfpga/src/echo_arch.cpp#L234-L238
we hope to implement adder using the hard adder instead of luts, however , the packer rise an error. #### Expected Behaviour our adder should be packed without any error...
The window of outline does not show the correct port signal but shows the type of signal. Just as follows.  OS: win10 VSCODE: 1.86.2 TerosHDL:5.0.12
terosHDL does not autocomplete port signals when I work in win11， However, terosHDL works well when I connect my Ubuntu server by SSH extension. Two environments have the same version...
@tangxifan In [online document](https://openfpga.readthedocs.io/en/master/manual/arch_lang/addon_vpr_syntax/), I have seen that layout has an attribution of `concat_wire`. However, the wire connecting doesn't have any difference whether `concat_wire` is disabled or not(the two pictures...
There is a bug that puzzles me a lot, and OpenFPGA does not raise any error while the bitstream seems not correct. I have a name.blif file, and its contents...
Hello, I had read your paper, "A Study on Switch Block Patterns for Tileable FPGA Routing Architectures", which mentioned some constraints to tileable routing. First of all, $W = \Sigma...
The top_left is a shortcut to define the organization for all the tiles. [Fig. 74](https://openfpga.readthedocs.io/en/master/manual/file_formats/tile_config_file/#fig-tile-style-top-left) shows an example of tiles in the top-left style, where the programmable block locates in...